WP #1 - Numerical methods and FPGA programming training
Training in numerical methods includes programming in direct and iterative methods for linear and nonlinear systems, evaluation of stability and accuracy of numerical algorithms and design and implementation of numerical algorithms in suitable software environment. Training in FPGA basics and programming includes familiarization with the FPGA architectures, VHDL or Verilog basics, while it completes with DSP concepts, algorithms and techniques for implementation. The researcher's training will be focused on those architectural features that improve design performance for reservoir computing (RC).
WP #1
WP #2
WP #2 - Concepts of RCs applied in optical communications and sensing networks
In this task, the investigation of RC properties exploiting the nonlinear dynamics of semiconductor-based devices or the appropriately programmed FPGA-based modules will be performed. These two distinct signal processing categories will be evaluated and compared in terms of implementation complexity, capability to provide nonlinear transfer functions that are useful for RC computation tasks and overall performance. The output of this task is to provide evidence that programmed modules or physical devices in a reservoir computing topology can overcome network routing and switching issues at high speed. Training and classification modules that effectively discriminate multi-bit header patterns are provisioned to be the first step to the entirely all-optical header recognition and ultrafast data switching and routing.
WP #3 - RCs implementations in optical communications and sensing networks
The most prominent topologies will be experimentally demonstrated and evaluated, initially as a standalone RC unit and thence in the imposed application problems. For the all-optical routing/switching telecom applications, several parameters that are associated to the operational performance will be evaluated: the supported bit-rate operation, the signal-to-noise ratio (SNR) restrictions on the input signal, the pre- and post- processing of the input signal in order to fit with the requirements of the RC system, the memory capacity of the reservoir, the total delay imposed from the RC decision process, the effect on bandwidth limitation of the RC process, etc. Target is to demonstrate error-free pattern recognition and classification of at least eight header patterns at Gb/s rates. Applying the same concept in sensor networks, we will deal with the "big data problem" established by conventional fiber-optic sensors - such as FBG-based sensors- that do not have any intelligence to support event-driven activation and device-controlled data transmission. Even though the information that the usual data packets carry is of low volume, real time monitoring techniques practically establish relentless data traffic from these sensors. RC at appropriate traffic nodes will be able to reduce dramatically the traffic of useful data sent by common unintelligent distant fiber-based sensors. Target is to demonstrate efficient drop-off of redundant data from high-volume bit streams and event-driven operation of these sensor networks.
